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HI20201
August 1997
10-Bit, 160 MSPS, Ultra High Speed D/A Converter
Description
The HI20201 is a 160MHz ultra high speed D/A converter. The converter is based on an R/2R switched current source architecture that includes an input data register with a complement feature and is Emitter Coupled Logic (ECL) compatible. The HI20201 is available in a commercial temperature range and offered in a 28 lead plastic SOIC (300 mil) and a 28 lead plastic DIP package.
Features
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz * Resolution (HI20201) . . . . . . . . . . . . . . . . . . . . . . . 10-Bit * Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB * Low Glitch Noise * Analog Multiplying Function * Low Power Consumption . . . . . . . . . . . . . . . . . .420mW * Evaluation Board Available * Direct Replacement for Sony CX20201-1, CX20202-1
Ordering Information
PART NUMBER HI20201JCB HI20201JCP HI20201-EV TEMP. RANGE (oC) -20 to 75 -20 to 75 25 PACKAGE 28 Ld SOIC 28 Ld PDIP Evaluation Kit PKG. NO. M28.3A-S E28.6A-S
Applications
* Wireless Communications * Signal Reconstruction * Direct Digital Synthesis * High Definition Video Systems * Digital Measurement Systems * Radar
Pinout
HI20201 (PDIP, SOIC) TOP VIEW
(MSB) D9 1 D8 2 D7 3 D6 4 D5 5 D4 6 D3 7 D2 8 D1 9 (LSB) D0 10 NC 11 NC 12 CLK 13 CLK 14 28 AVSS 27 VREF 26 AVEE 25 NC 24 NC 23 NC 22 NC 21 NC 20 IOUT 19 NC 18 AVSS 17 DVSS 16 COMPL 15 DVEE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3581.5
10-1197
HI20201 Typical Application Circuit
HI20201 (28) AVSS 1.5k 1k (27) VREF 2k (26) AVEE TL431CP -5.2V 0.047F 1.0F
D9 D8 D7 D6 DIGITAL DATA (ECL) D5 D4 D3 D2 D1 D0
D9 (MSB) (1) D8 (2) D7 (3) D6 (4) D5 (5) D4 (6) D3 (7) D2 (8) D1 (9) D0 (LSB) (10) (11) (12)
.
~2.7V
75 COAX CABLE (20) IOUT (18, 19, 21-25) NC D/A OUT
82 CLK -1.3V 131
82 CLK (13) CLK (14) (17) DVSS (16) COMPL (15) DVEE 1.0F 0.047F -5.2V 3.6k
131 -5.2V
Functional Block Diagram
(LSB) D0 D1 D2 D3 D4 D5 D6 15 D7 D8 (MSB) D9 UPPER 4-BIT ENCODER 15 15 15 15 15 15 SWITCHED CURRENT CELLS IOUT INPUT BUFFER 15 8-BIT REGISTER 15 6 LSBs CURRENT CELLS R/2R NET/WORK
COMPL CLK CLK CLOCK BUFFER BIAS CURRENT GENERATOR VREF
10-1198
HI20201
Absolute Maximum Ratings
Digital Supply Voltage DVEE to DVSS . . . . . . . . . . . . . . . . . . . -7.0V Analog Supply Voltage AVDD to AVSS . . . . . . . . . . . . . . . . . . -7.0V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DVEE V Reference Input Voltage . . . . . . . . . . . . . . . . . . . . . . +0.3 to AVEE V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V Digital Input Voltage VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V Reference Input Voltage, VREF . . . . . . . . VEE + 0.5V to VEE + 1.4V Load Resistance, RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Output Voltage, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-20oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = 25oC, AVEE = DVEE = -5.2V, AGND = DGND = 0V, RL = , VOUT = -1V HI20201JCB/JCP
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, VOS (Adjustable to Zero) Full Scale Error, FSE (Adjustable to Zero) Full Scale Output Current, IFS DYNAMIC CHARACTERISTICS Throughput Rate Glitch Energy, GE REFERENCE INPUT Voltage Reference Input Range Reference Input Current Voltage Reference to Output Small Signal Bandwidth Output Rise Time, tr Output Fall Time, tf DIGITAL INPUTS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Input Logic Current, IIL , IIH (For D9 thru D6, COMPL)
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10 fS = 160MHz (End Point) fS = 160MHz (Note 3) (Note 3) -
7 -
1.0 0.50 102 20
Bits LSB LSB LSB LSB mA
See Figure 11 ROUT = 75 With Respect to AVEE VREF = -4.58V -3dB point 1VP-P Input RLOAD = 75 RLOAD = 75 (Note 2) (Note 2) VIH = -0.89V, VIL = -1.75V (Note 2)
160 -
15
-
MHz pV/s
+0.5 -0.1 -
-0.4 14.0 1.5 1.5
+1.4 -3.0 -
V A MHz ns ns
-1.0
-0.89 -1.75 -1.6 6.0 3.0
V V A A
0.1 0.1
1.5 0.75
Input Logic Current, IIL , IIH (For D5 thru D0) VIH = -0.89V, VIL = -1.75V (Note 2) TIMING CHARACTERISTICS Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD Settling Time, tSET (to 1/2 LSB) See Figure 11 See Figure 11 See Figure 11 See Figure 11
5 1 -
3.8 5.2
-
ns ns ns ns
10-1199
HI20201
Electrical Specifications
TA = 25oC, AVEE = DVEE = -5.2V, AGND = DGND = 0V, RL = , VOUT = -1V (Continued) HI20201JCB/JCP PARAMETER POWER SUPPLY CHARACTERISITICS IEE Power Dissipation NOTES: 2. Parameter guaranteed by design or characterization and not production tested. 3. Excludes error due to reference drift. 4. Electrical specifications guaranteed only under the stated operating conditions. 75 load -60 -75 420 -90 470 mA mW TEST CONDITIONS MIN TYP MAX UNITS
Timing Diagram
CLK CLK DATA
tSU N tD
tHD N+1 tD 90% 50% 10% tr tf N N+1
0V D/A OUT -1V
FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS)
Pin Descriptions
28 PIN SOIC 1-10 11, 12, 19, 21- 25 13 14 15 16 PIN NAME D0 (LSB)-D9 (MSB) NC CLK CLK DVEE COMPL PIN DESCRIPTION Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 9, the Most Significant Bit. No Connect, not used. Negative Differential Clock Input. Positive Differential Clock Input Digital (ECL) Power Supply -4.75V to -7V. Data Complement Pin. When set to a (ECL) logic High the input data is complemented in the input buffer. When cleared to a (ECL) logic Low the input data is not complemented. Digital Ground. Analog Ground. Current Output Pin. Analog Supply -4.75V to -7V. Input Reference Voltage used to set the output full scale range. Analog Ground.
17 18 20 26 27 28
DVSS AVSS IOUT AVEE VREF AVSS
10-1200
HI20201 Typical Performance Curves
-2.0 FULL SCALE OUTPUT VOLTAGE (V) TA = 25oC, VEE = -5.2V FULL SCALE OUTPUT VOLTAGE (RELATIVE VALUE) VO(FS)/(VO(FS) AT TA = 25oC) 1.05
LINEAR AREA RL = 10k -1.0
1.00
RL = 10k
RL = 75
RL = 75
0 0.5
1.0 VREF - VEE (V)
1.5
0.95 -20
0
20 40 60 AMBIENT TEMPERATURE (oC)
80
FIGURE 2. VO(FS) RATIO vs (VREF - VEE)
FIGURE 3. FULL SCALE OUTPUT VOLTAGE vs AMBIENT TEMPERATURE
0 10.0 GAIN GLITCH ENERGY (pV/s) 0 PHASE (DEGREE) 8.0
fCLK = 100MHz
GAIN (dB)
PHASE -10 -90
6.0
4.0
-180
2.0
-20 10K
100K 1M 10M MULTIPLYING INPUT SIGNAL FREQUENCY (Hz)
100M
-50
0 50 CASE TEMPERATURE (oC)
100
FIGURE 4. OUTPUT CHARACTERISTICS vs MULTIPLYING INPUT SIGNAL FREQUENCY
FIGURE 5. GLITCH ENERGY vs CASE TEMPERATURE (FULL SCALE - 1023mV)
10-1201
HI20201 Detailed Description
The HI20201 is a 10-bit, current output D/A converter. The DAC can run at 160MHz and is ECL compatible. The architecture is segmented/R2R combination to reduce glitch and improve linearity. Architecture The HI20201 is a combined R2R/segmented current source design. The 6 least significant bits of the converter are derived by a traditional R2R network to binary weight the 1mA current sources. The upper 4 most significant bits are implemented as segmented or thermometer encoded current sources. The encoder converts the incoming 4 bits to 15 control lines to enable the most significant current sources. The thermometer encoder will convert binary to individual control lines. See Table 1.
TABLE 1. THERMOMETER ENCODER THERMOMETER CODE 1 = ON, 0 = OFF, I15 - I0 000 0000 0000 0000 000 0000 0000 0001 000 0000 0000 0011 000 0000 0000 0111 000 0000 0000 1111 000 0000 0001 1111 000 0000 0011 1111 000 0000 0111 1111 000 0000 1111 1111 000 0001 1111 1111 000 0011 1111 1111 000 0111 1111 1111 000 1111 1111 1111 001 1111 1111 1111 011 1111 1111 1111 111 1111 1111 1111
A (mV) GLITCH ENERGY = (a x t)/2
01 1111 1111 to 10 0000 0000. But in the HI20201 the glitch is moved to the 00 0001 1111 to 11 1110 0000 transition. This is achieved by the split R2R/segmented current source architecture. This decreases the amount of current switching at any one time and makes the glitch practically constant over the entire output range. By making the glitch a constant size over the entire output range this effectively integrates this error out of the end application. In measuring the output glitch of the HI20201 the output is terminated into a 75 load. The glitch is measured at the major carry's throughout the DAC's output range.
HI20201 (20) IOUT 75 34MHz LOW PASS FILTER SCOPE
MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
BIT 8 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
BIT 7 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
BIT 6 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
50
FIGURE 6. HI20201 GLITCH TEST CIRCUIT
The glitch energy is calculated by measuring the area under the voltage-time curve. Figure 7 shows the area considered as glitch when changing the DAC output. Units are typically specified in picoVolt/seconds (pV/s).
The architecture of the HI20201 is designed to minimize glitch while providing a manufacturable 10-bit design that does not require laser trimming to achieve good linearity. Glitch Glitch is caused by the time skew between bits of the incoming digital data. Typically the switching time of digital inputs are asymmetrical meaning that the turn off time is faster than the turn on time (TTL designs). In an ECL system where the logic levels switch from one non-saturated level to another, the switching times can be considered close to symmetrical. This helps to reduce glitch in the D/A. Unequal delay paths through the device can also cause one current source to change before another. To minimize this the Intersil HI20201 employs an internal register, just prior to the current sources, that is updated on the clock edge. Lastly the worst case glitch usually happens at the major transition i.e.,
t (ns)
FIGURE 7. GLITCH ENERGY
Setting Full Scale The full scale output voltage is set by the Voltage Reference pin (27). The output voltage performance will vary as shown in Figure 2. The output structure of the HI20201 can handle down to a 75 load effectively. To drive a 50 load Figure 8 is suggested. Note the equivalent output load is ~75.
10-1202
HI20201
Clock Phase Relationship The HI20201 is designed to be operated at very high speed (i.e., 160MHz). The clock lines should be driven with ECL100K logic for full performance. Any external data drivers and clock drivers should be terminated with 50 to minimize reflections and ringing. Internal Data Register
(18, 19, 21-25) NC
HI20201 39 (20) IOUT 50 COAX CABLE D/A OUT 100
FIGURE 8. HI20201 DRIVING A 50 LOAD
The HI20201 incorporates a data register as shown in the Functional Block Diagram. This register is updated on the rising edge of the CLK line. The state of the Complement bit (COMPL) will determine the data coding. See Table 2.
TABLE 2. INPUT CODING TABLE OUTPUT CODE INPUT CODE 00 0000 0000 10 0000 0000 11 1111 1111 COMPL = 1 0 -0.5 -1 COMPL = 0 -1 -0.5 0
Variable Attenuator Capability The HI20201 can be used in a multiplying mode with a variable frequency input on the VREF pin. In order for the part to operate correctly a DC bias must be applied and the incoming AC signal should be coupled to the VREF pin. See Figure 13 for the application circuit. The user must first adjust the DC reference voltage. The incoming signal must be attenuated so as not to exceed the maximum (+1.4V) and minimum (+0.5V) reference input. The typical output Small Signal Bandwidth is 14MHz. Integral Linearity The Integral Linearity is measured using the End Point method. In the End Point method the gain is adjusted. A line is then established from the zero point to the end point or Full Scale of the converter. All codes along the transfer curve must fall within an error band of 1 LSB of the line. Figure 10 shows the linearity test circuit. Differential Linearity The Differential Linearity is the difference from the ideal step. To guarantee monotonicity a maximum of 1 LSB differential error is allowed. When more than 1 LSB is specified the converter is considered to be missing codes. Figure 10 shows the linearity test circuit.
Thermal Considerations The temperature coefficient of the full scale output voltage and zero offset voltage depend on the load resistance connected to IOUT . The larger the load resistor, the better (i.e., smaller) the temperature coefficient of the D/A. See Figure 3 in the performance curves section. Noise Reduction Digital switching noise must be minimized to guarantee system specifications. Since 1 LSB corresponds to 1mV for 10-bit resolution, care must be taken in the layout of a circuit board. Separate ground planes should be used for DVSS and AVSS . They should be connected back at the power supply. Separate power planes should be used for DVEE and AVEE . They should be decoupled with a 1F tantalum capacitor and a ceramic 0.047F capacitor positioned as close to the body of the IC as possible.
10-1203
HI20201 Test Circuits
a b a b a b a b a b a b a b a b a b a b
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 1 2 3 4 5 6 7 8 9 10 11 12 28 27 26 25 24 23 22 21 S19 20 19 18 17 S17 16 15 5.2V 1mA
a
S20 b S16 a I1 5.2V
a b
I6 4.56V
b
I2 S11
a
-0.89V
b
-1.75V
a b
V1
-0.89V OR -1.75V
a S14 I3 b a S15 I4 b
-0.89V -1.75V
a S12 13 b a S13 14 b
a b
I5
S18 a
b
FIGURE 9. CURRENT CONSUMPTION, INPUT CURRENT AND OUTPUT RESISTANCE
LINEARITY ERRORS ARE MEASURED AS FOLLOWS S1 0 0 0
10K 5.2V 4 5 6 7 8 9 10 11 12 1.3V 1 SHOT CLK 13 14 25 24 23 22 21 20 19 18 17 16 5.2V 15 V0 D/A OUT
"1"
S1 S2 S3 S4 S5 S6
1 2 3
28
27 26
S2 0 0 0
S3 0 0 0
"0" 0.89V 1.75V
1
1
1
**** **** **** **** * * * ****
S9 0 0 1
S10 0 1 0
1
1
D/A OUT V0 V1 V2 * * * V1023
INTEGRAL LINEARITY ERROR V0 V1 V2 V4 V8 V16 V32 V64 V128 V192 * * * V960 V1023
DIFFERENTIAL LINEARITY ERROR V1 - V0 V2 - V1 V4 - V3 V8 - V7 V16 - V15 V32 - V31 V64 - V63 V128 - V127 V192 - V191 * * * V960 - V959
10-BIT DATA
S7 S8 S9 S10
Adjust so that the full scale of DC voltage at pin 20 becomes
1.023V, that is, to satisfy VO - V1023 = 1.023V.
Error at individual measurement points are calculated according to the following definition. (V1023 - V0)/1023 = V0(FS)/1023 1 LSB.
FIGURE 10. DIFFERENTIAL LINEARITY ERROR AND LINEARITY ERROR
10-1204
HI20201 Test Circuits
(Continued)
1/ HD100151 6
B 10k 82 1 2 MSB 28 27 26 25 24 23 22 21 OUT 20 19 18 17 16 15 -5.2V TO SCOPE 100 C 39 -5.2V
82
D 131
Q Q 131 -5.2V
3 4 5 6 7
-5.2V CLKF TO PG -1.3V 50 1 HD100116 1
8 9 82 CLKF 10 LSB 11 12 A 13 CLK 1 14 CLK 131 131 -5.2V 131
50
470 DL
131
82
82
-1.3V
DL: Delay line Capacitors are 0.047F ceramic chip capacitors unless otherwise specified.
FIGURE 11. MAXIMUM CONVERSION RATE, RISE TIME, FALL TIME, PROPAGATION DELAY, SETUP TIME, HOLD TIME AND SETTLING TIME CIRCUIT
Measuring Settling Time Settling time is measured as follows. The relationship between V and V0(FS) as shown in the D/A output waveform in Figure 12 is expressed as V = V0(FS) (1 - e-t). The settling time for respective accuracy of 10, 9 and 8-bit is specified as V = 0.9995 V0(FS) V = 0.999 V0(FS) V = 0.999 V0(FS) which results in the following: tS = 7.60 tS = 6.93 tS = 6.24 for 10-bit, for 9-bit, and for 8-bit,
V V0(FS) = 1V
Rise time (tr) and fall time (tf) are defined as the time interval to slew from 10% to 90% of full scale voltage (V0(FS)): V = 0.1 V0(FS) V = 0.9 V0(FS) and calculated as tr = tf = 2.20. The settling time is obtained by combining these expressions: tS = 3.45tr tS = 3.15tr tS = 6.24tr for 10-bit, for 9-bit, and for 8-bit
FIGURE 12. D/A OUTPUT WAVEFORM
10-1205
HI20201 Test Circuits
(Continued) Adjust so that the voltage at point B becomes -1V with no AC input.
"1" 1 2 3 4 5 6 7 8 9 10 11 12 CLK CLK 13 14 28 27 0.047 26 25 24 23 22 21 20 19 18 17 16 15 -5.2V A GND D GND B TO SCOPE A -5.2V 51 10k 0.1F OSC
FIGURE 13A.
WAVEFORM AT POINT A
VEE -0.62V VEE -0.31V
FIGURE 13B.
WAVEFORM AT POINT B
1VP-P AT 1MHz -1V
FIGURE 13C. FIGURE 13. MULTIPLYING BANDWIDTH
10-1206
HI20201
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
10-1207

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